RISC-V SoC Tape-Out
Chip Design RISC-V Cadence
Hardware redaction techniques applied to RISC-V SoC in Cadence (TSMC180)
Design & Code
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Purdue ECE
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Hardware redaction techniques applied to RISC-V SoC in Cadence (TSMC180)
FPGA-based testing framework with XOR methodology and Hamming distance analysis
Runtime-reconfigurable FIR filter on AMD Kria KV260
Non-optical wearable controller with haptic feedback and sensor fusion
Magnetic Tunnel Junction arrays for MRAM research